The invention relates to the transfer of data via DMA between a system resource and a controller via switching logic.
In computer systems, blocks of data can be quickly transferred between a system resource and a system memory via DMA using a controller. Before the DMA transfer can begin, certain information must be provided for use by the system resource and the controller.
In general, the starting addresses that will be accessed by the system resource and by the memory are stored in pointer registers. The addresses stored in the pointer registers are incremented or decremented by the system resource and by the controller to access the appropriate storage locations. As a result, an entire block of data can be transferred without the intervention of the main processors in the computer system.
A byte or word count also is provided and is stored in a counter before the DMA transfer begins. The count changes as each byte or word of DMA data is transferred. When the counter determines that all of the bytes or words in the DMA data block have been transferred, the DMA operation is complete.
In many computer systems, multiple system resources are present that can perform DMA transfers with a system memory. In these systems, switching logic is necessary in order to couple a particular system memory to a selected system resource.
However, in systems containing switching logic, it may be difficult to set up the required data path rapidly for an imminent DMA data transfer. The difficulty increases if the switching logic must be configured to allow DMA data to be transferred in a either of two directions between the selected system resource and the system memory.
Therefore, there is a need for a computer system in which the switching logic is efficiently set up before a DMA transfer starts to enable DMA data to be transferred between a particular system memory and a selected system resource. There also is a need for a computer system in which a simple protocol is used to rapidly initialize the pointer registers, counters, and switching logic in preparation for a DMA transfer.